Empirical evaluation of the resistance of novel non-algebraic AES s-boxes to power side-channel attacks

In the area of hardware security, the exploitation of Side-Channel Analysis (SCA) to attack hardware devices has become a major issue in the last 20 years. The study of effective countermeasures is crucial, as this class of attacks reaches higher rates of effectiveness with respect to classical cryptanalysis. While implementation-level countermeasures are achieving promising results, the academic community has recently focused on solutions that can reduce leakage from the cryptographic mathematical layer, regardless of the underlying hardware/software architecture. In the field of symmetric encryption schemes (such as AES), novel substitution structures have been proposed, claiming an improved side-channel resistance without any additional costs in terms of area, performance or power consumption. To the best of our knowledge, most of these solutions have been studied only from a mathematical point of view, and are still lacking practical experimentation on resource-constrained devices. This paper provides an empirical evaluation of the latest S-Box proposals. The necessary data has been collected in a reference scenario with limited noise effects, targeting an unprotected software implementation of the AES-128 algorithm running on an 8-bit microcontroller. The results indicate that, despite claims of enhanced resistance to Side-Channel Analysis, these new countermeasures do not offer a meaningful improvement over the standard AES implementation and are insufficient to prevent a successful attack. Moreover, when compared to widely known implementation-level countermeasures such as masking and hiding, these novel approaches appear far less promising: established techniques provide substantially stronger protection in practice for implementations capable of supporting them.